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may 2011 doc id 15609 rev 3 1/37 1 vn5e160as-e single channel high side driver with analog for automotive applications features general ? inrush current active management by power limitation ? very low standby current ? 3.0 v cmos compatible inputs ? optimized electromagnetic emission ? very low electromagnetic susceptibility ? in compliance with the 2002/95/ec european directive ? very low current sense leakage diagnostic functions ? proportional load current sense ? high-precision current sense for wide-range currents ? current sense disable ? off-state open-load detection ? output short to v cc detection ? overload and short to ground (power limitation) indication protections ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self-limiting of fast thermal transients ? protection against loss of ground and loss of v cc ? overtemperature shutdown with autorestart (thermal shutdown) ? reverse battery protected ? electrostatic discharge protection application all types of resistive, inductive and capacitive loads suitable as led driver description the vn5e160as-e is a single-channel high-side driver manufactured in the st proprietary vipower? m0-5 technology and housed in the tiny so-8 package. the vn5e160as-e is designed to drive 12 v automotive grounded loads delivering protection, diagnostics and easy 3 v and 5 v cmos compatible interface with any microcontroller. the device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto-restart and overvoltage active clamp. a dedicated analog current sense pin is associated with every output channel in order to provide ehnanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication, overtemperature indication, short-circuit to v cc diagnosis and on & off state open-load detection. the current sensing and diagnostic feedback of the whole device can be disabled by pulling the cs_dis pin high to allow sharing of the external sense resistor with other similar devices. max supply voltage v cc 41 v operating voltage range v cc 4.5 v to 28 v max on-state resistance (per ch.) r on 160 m current limitation (typ) i limh 10 a off-state supply current i s 2 a (1) 1. typical value with all loads connected. 62 ("1($'5 www.st.com
contents vn5e160as-e 2/37 doc id 15609 rev 3 contents 1 block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24 3.1.1 solution 1: resistor in the ground line (rgnd only) . . . . . . . . . . . . . . . . 24 3.1.2 solution 2: a diode (dgnd) in the ground line . . . . . . . . . . . . . . . . . . . 25 3.2 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 mcu i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.1 short to vcc and off-state open load detection . . . . . . . . . . . . . . . . . 27 3.5 maximum demagnetization energy (vcc = 13.5 v) . . . . . . . . . . . . . . . . . 28 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 so-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
vn5e160as-e list of tables doc id 15609 rev 3 3/37 list of tables table 1. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. switching (v cc = 13 v; tj = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. current sense (8 v < v cc < 18 v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 10. openload detection (8 v < v cc < 18 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 11. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 16. so-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of figures vn5e160as-e 4/37 doc id 15609 rev 3 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. off-state open-load delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. delay response time between rising edge of ouput current and rising edge of current sense (cs enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. i out /i sense vs i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. maximum current sense ratio drift vs load current (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. overload or short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14. off-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 15. short to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. t j evolution in overload or short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. high-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 19. input voltage clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 20. low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 21. high-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 22. hysteresis input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 23. on-state resistance vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 24. on-state resistance vs. v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 25. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 26. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 27. i limh vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 28. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 29. high-level cs_dis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 30. cs_dis voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 31. low-level cs_dis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 32. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 33. current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 34. maximum turn-off current versus inductance (for each channel) (1) . . . . . . . . . . . . . . . . . . 28 figure 35. so-8 pc board (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 36. rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 29 figure 37. so-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 38. thermal fitting model of an hsd in so-8 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 39. so-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 40. so-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 41. so-8 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4
vn5e160as-e block diagram and pin configuration doc id 15609 rev 3 5/37 1 block diagram and pin configuration figure 1. block diagram table 1. pin function name function v cc battery connection. out power output. gnd ground connection. must be reverse battery protected by an external diode/resistor network. in voltage-controlled input pin with hysteresis, cmos compatible. controls output switch state. cs analog current sense pin, delivers a current proportional to the load current. cs_dis active high cmos compatible pin, to disable the current sense pin. 6 ## #ontrol$iagnostic ,/')# $2)6%2 6 /. ,imitation #urrent ,imitation 0ower #lamp /&&3tate /penload /ver temperature 5ndervoltage 6 3%.3%( #urrent 3ense /6%2,/!$02/4%#4)/. !#4)6%0/7%2,)-)4!4 )/. ). #3 #3? $)3 '.$ /54 3ignal#lamp '!0'#&4
block diagram and pin configuration vn5e160as-e 6/37 doc id 15609 rev 3 figure 2. configuration diagram (top view) table 2. suggested connections for unused and not connected pins connection / pin current sense n.c. output input cs_dis floating not allowed x x x x to ground through 1 k resistor x not allowed through 10 k resistor through 10 k resistor 6 ## 6 ## /54 /54 #3?$)3 '. $ #3 ). 3/ '!0'#&4
vn5e160as-e electrical specifications doc id 15609 rev 3 7/37 2 electrical specifications figure 3. current and voltage conventions (1) 1. v f = v out - v cc during reverse battery condition. 2.1 absolute maximum ratings stressing the device above the ratings listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to the conditions in the ?absolute maximum ratings? table for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. ) 3 ) '.$ 6 ## 6 ## 6 3%.3% /54 ) /54 #3 ) 3%.3% ). ) ). 6 ). 6 /54 '.$ #3?$) 3 ) #3$ 6 #3$ 6 & '!0'#&4 table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v -v cc reverse dc supply voltage 0.3 v - i gnd dc reverse ground pin current 200 ma i out dc output current internally limited a - i out reverse dc output current 6 a i in dc input current -1 to 10 ma i csd dc current sense disable input current -1 to 10 ma -i csense dc reverse cs pin current 200 ma v csense current sense maximum voltage v cc -41 +v cc v v
electrical specifications vn5e160as-e 8/37 doc id 15609 rev 3 2.2 thermal data e max maximum switching energy (single pulse) (l = 8 mh; r l = 0 ; v bat = 13.5 v; t jstart = 150 c; i out = i liml (typ.) ) 36 mj v esd electrostatic discharge (human body model: r = 1.5 k ; c = 100 pf) ?in ?cs ?cs_dis ?out ?v cc 4000 2000 4000 5000 5000 v v v v v v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 c table 3. absolute maximum ratings (continued) symbol parameter value unit table 4. thermal data symbol parameter max value unit r thj-pins thermal resistance junction-pins 30 c/w r thj-amb thermal resistance junction-ambient see figure 36 c/w
vn5e160as-e electrical specifications doc id 15609 rev 3 9/37 2.3 electrical characteristics values specified in this section are for 8 v < v cc < 28 v; -40 c < tj < 150 c, unless otherwise stated. table 5. power section symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 4.5 13 28 v v usd undervoltage shut-down 3.5 4.5 v v usdhyst undervoltage shut-down hysteresis 0.5 v r on on-state resistance i out = 1 a, t j = 25 c 160 m i out = 1 a, t j = 150 c 320 i out = 1 a, v cc = 5 v, t j = 25 c 210 v clamp voltage clamp i s = 20 ma 41 46 52 v i s supply current off-state: v cc = 13 v, v in =v out =0v, t j =25c 2 (1) 1. powermos leakage included. 5 (1) a on-state: v in =5v, v cc =13v, i out =0a 1.9 3.5 ma i l(off1) off-state output current v in =v out =0v, v cc =13v, t j =25c 00.01 3 a v in =v out =0v, v cc =13v, t j =125c 05 v f output - v cc diode voltage -i out =1a, t j =150c 0.7 v table 6. switching (v cc =13 v; t j =25 c) symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time r l =13 (see figure 6 ) ?10?s t d(off) turn-off delay time r l =13 (see figure 6 ) ?10?s dv out /dt (on) turn-on voltage slope r l = 13 ? see figure 26 ?v/s dv out /dt (off) turn-off voltage slope r l = 13 ? see figure 28 ?v/s w on switching energy losses during t won r l =13 (see figure 6 ) ?0.05?mj w off switching energy losses during t woff r l =13 (see figure 6 ) ?0.03?mj
electrical specifications vn5e160as-e 10/37 doc id 15609 rev 3 table 7. logic inputs symbol parameter test conditions min. typ. max. unit v il low-level input voltage 0.9 v i il low-level input current v in = 0.9 v 1 a v ih high-level input voltage 2.1 v i ih high-level input current v in = 2.1 v 10 a v i(hyst) hysteresis input voltage 0.25 v v icl input voltage clamp i in = 1 ma 5.5 7 v i in = -1 ma -0.7 v csdl low-level cs_dis voltage 0.9 v i csdl low-level cs_dis current v csd = 0.9 v 1 a v csdh high-level cs_dis voltage 2.1 v i csdh high-level cs_dis current v csd = 2.1 v 10 a v csd(hyst) hysteresis cs_dis voltage 0.25 v v cscl cs_dis voltage clamp i csd = 1 ma 5.5 7 v i csd = -1 ma -0.7 table 8. protection and diagnostics (1) 1. to ensure long term reliability under heavy overload or short circuit conditions , protection and related diagnostic signals must be used together with a proper soft ware strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. symbol parameter test conditions min. typ. max. unit i limh dc short-circuit current v cc = 13 v 7 10 14 a 5 v < v cc < 28 v 14 a i liml short-circuit current during thermal cycling v cc = 13 v t r < t j < t tsd 2.5 a t tsd shutdown temperature 150 175 200 c t r reset temperature t rs + 1 t rs + 5 c t rs thermal reset of status 135 c t hyst thermal hysteresis (t tsd - t r ) 7c v demag turn-off output voltage clamp i out =1a, v in =0, l=20mh v cc -41 v cc -46 v cc -52 v v on output voltage drop limitation i out = 0.03 a (see figure 8 ) t j = -40 c to +150 c 25 mv
vn5e160as-e electrical specifications doc id 15609 rev 3 11/37 table 9. current sense (8 v < v cc < 18 v) symbol parameter test conditions min. typ. max. unit k 0 i out /i sense i out =0.025a, v sense =0.5v t j = -40 c to 150 c 265 490 715 k 1 i out /i sense i out = 0.35 a, v sense = 0.5 v t j = -40 c to 150 c t j = 25 c to 150 c 355 385 465 465 575 545 dk 1 /k 1 (1) current sense ratio drift i out =0.35 a, v sense = 0.5 v t j = -40 c to 150 c -11 +11 % k 2 i out /i sense i out = 0.5 a, v sense = 4 v t j = -40 c to 150 c t j = 25 c to 150 c 380 400 455 455 530 510 dk 2 /k 2 (1) current sense ratio drift i out = 0.5 a; t j = -40 c to 150 c -8 +8 % k 3 i out /i sense i out = 1.5 a, v sense = 4 v t j = -40 c to 150 c t j = 25 c to 150 c 420 420 455 455 490 480 dk 3 /k 3 (1) current sense ratio drift i out = 1.5 a; t j = -40 c to 150 c -4 +4 % i sense0 analog sense leakage current i out = 0 a, v sense = 0 v, v csd = 5 v, v in = 0 v, t j = -40 c to 150 c 01 a i out = 0 a, v sense = 0 v, v csd = 0 v, v in = 5 v, t j = -40 c to 150 c 02 i out = 1 a, v sense = 0 v, v csd = 5 v, v in = 5 v, t j = -40 c to 150 c 01 v sense max analog sense output voltage r sense = 10 k i out = 1 a; 5v v senseh (2) analog sense output voltage in fault condition v cc = 13 v, r sense = 3.9 k 8v i senseh (2) analog sense output current in fault condition v cc = 13 v, v sense = 5 v 9 ma t dsense1h delay response time from falling edge of cs_dis pin v sense < 4 v, 0.025 a < i out <1.5a i sense = 90% of i sense max (see figure 4 ) 40 100 s t dsense1l delay response time from rising edge of cs_dis pin v sense < 4 v, 0.025 a < i out <1.5a i sense = 10% of i sense max (see figure 4 ) 520s
electrical specifications vn5e160as-e 12/37 doc id 15609 rev 3 t dsense2h delay response time from rising edge of in pin v sense < 4 v, 0.025 a < i out <1.5a i sense =90% of i sense max (see figure 4 ) 30 160 s t dsen se 2h delay response time between rising edge of output current and rising edge of current sense v sense <4 v, i sense = 90% of i sensemax, i out = 90% of i outmax i outmax =1.5a (see figure 7 ) 110 s t dsense2l delay response time from falling edge of in pin v sense <4v, 0.025 a < i out <1.5a i sense =10% of i sense max (see figure 4 ) 80 250 s 1. parameter guaranteed by design; it is not tested. 2. fault condition includes: power limitation, ov ertemperature and open load off-state detection. table 10. openload detection (8 v < v cc < 18 v) symbol parameter test conditions min. typ. max. unit v ol off-state open-load voltage detection threshold v in = 0 v, 8 v < v cc < 18 v 2 4 v i ol on-state open-load current detection threshold v in = 5v, 8 v < v cc < 18 v i sense = 5 a 0.5 5 ma t dstkon output short-circuit to v cc detection delay at turn-off see figure 5 180 1200 s i l(off2)r off-state output current at v out = 4 v v in = 0 v, v sense = 0 v v out rising from 0 v to 4 v -120 0 a i l(off2)f off-state output current at v out = 2 v v in = 0 v, v sense = v senseh v out falling from v cc to 2 v -50 90 td_vol delay response from output rising edge to v sense rising edge in open-load v out = 4 v, v in = 0 v v sense = 90% of v senseh 20 s table 9. current sense (8 v < v cc < 18 v) (continued) symbol parameter test conditions min. typ. max. unit
vn5e160as-e electrical specifications doc id 15609 rev 3 13/37 figure 4. current sense delay characteristics figure 5. off-state open-load delay timing figure 6. switching characteristics 6(16(&855(17 ,1387 /2$'&855(17 &6b',6 w '6(16(+ w '6(16(/ w '6(16(/ w '6(16(+ $*9 9 287 !9 2/ 9 6(16(+ 9 ,1 9 &6 w '67.21 2xwsxwvwxfndw9 && *$3*&)7 9 287 g9 287 gw rq w u w i w grii ,1387 w w w grq g9 287 gw rii *$3*&)7 w :rq w :rii
electrical specifications vn5e160as-e 14/37 doc id 15609 rev 3 figure 7. delay response time between rising edge of ouput current and rising edge of current sense (cs enabled) figure 8. output voltage drop limitation 9 ,1 , 287 , 6(16(0$; ?w '6(16(+ w w w , 6(16(0$; , 2870$; , 2870$; , 6(16( $*9 9 21 , 287 7 m ?& 7 m ?& 7 m ?& 9 21 5 21 7 9 && 9 287 $*9
vn5e160as-e electrical specifications doc id 15609 rev 3 15/37 figure 9. i out /i sense vs i out figure 10. maximum current sense ratio drift vs load current (1) 1. parameter guaranteed by design; it is not tested. a : max, t j = -40 c to 150 c b : max, t j = 25 c to 150 c c : typical, t j = -40 c to 150 c d : min, t j = 25 c to 150 c e : min, t j = -40 c to 150 c i out /i sense 320 350 380 410 440 470 500 530 560 590 620 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 i out (a) a b c d e a : max, t j = -40 c to 150 c b : min, t j = 25 c to 150 c dk/k (%) -15 -12 -9 -6 -3 0 3 6 9 12 15 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 i out (a) a b
electrical specifications vn5e160as-e 16/37 doc id 15609 rev 3 table 11. truth table conditions in out sense (v csd = 0 v) (1) 1. if the v csd is high, the sense output is at a high impedance, its potential depends on leakage currents and external circuit. normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overload h h x (no power limitation) cycling (power limitation) nominal v senseh short circuit to gnd (power limitation) l h l l 0 v senseh off-state open-load (with external pull-up) lhv senseh
vn5e160as-e electrical specifications doc id 15609 rev 3 17/37 table 12. electrical transient requirements (part 1) iso 7637-2: 2004(e) test pulse test levels (1) number of pulses or test times burst cycle/pulse repetition time delays and impedance iii iv 1 -75 v -100 v 5000 pulses 0.5 s 5 s 2 ms, 10 2a +37 v +50 v 5000 pulses 0.2 s 5 s 50 s, 2 3a -100 v -150 v 1h 90 ms 100 ms 0.1 s, 50 3b +75 v +100 v 1h 90 ms 100 ms 0.1 s, 50 4 -6 v -7 v 1 pulse 100 ms, 0.01 5b (2) +65 v +87 v 1 pulse 400 ms, 2 table 13. electrical transient requirements (part 2) iso 7637-2: 2004(e) test pulse test level results (1) 1. the above test levels must be considered referred to v cc = 13.5 v except for pulse 5b iii iv 1c c 2a c c 3a c c 3b c c 4c c 5b (2) 2. valid in case of external load dump clamp: 40 v maximum referred to ground. cc table 14. electrical transient requirements (part 3) class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
electrical specifications vn5e160as-e 18/37 doc id 15609 rev 3 2.4 waveforms figure 11. normal operation figure 12. overload or short to gnd , 287 9 6(16( 9 &6b',6 ,1387 1rplqdoordg 1rplqdoordg 1rupdorshudwlrq $*9 3rzhu/lplwdwlrq , /lp+ ! , /lp/ ! 7khupdof\folqj 2yhuordgru6kruwwr*1' , 287 9 6(16( 9 &6b',6 ,1387 $*9
vn5e160as-e electrical specifications doc id 15609 rev 3 19/37 figure 13. intermittent overload figure 14. off-state open-load with external circuitry ! 1rplqdoordg ,qwhuplwwhqw2yhuordg ! 2yhuordg ! , 287 9 6(16( 9 &6b',6 ,1387 9 6(16(+ , /lp+ , /lp/ $*9 2)) 6wdwh2shq/rdg zlwkh[whuqdoflufxwu\ ! , 287 9 6(16( 9 &6b',6 ,1387 9 287 $*9 9 2/ 9 287 !9 2/ 9 6(16(+ w '67.rq
electrical specifications vn5e160as-e 20/37 doc id 15609 rev 3 figure 15. short to v cc figure 16. t j evolution in overload or short to gnd w '67.rq 5hvlvwlyh 6kruwwr9 && +dug 6kruwwr9 && 6kruwwr9 && , 287 9 287 9 &6b',6 9 2/ 9 287 !9 2/ w '67.rq $*9 7 - hyroxwlrqlq 2yhuordgru6kruwwr*1' , /lp+ ! 3rzhu/lplwdwlrq 6hoiolplwdwlrqriidvwwkhupdowudqvlhqwv ,1387 7 - , 287 7 -b67$57 7 5 7 76' 7 +<67 , /lp/ $*9
vn5e160as-e electrical specifications doc id 15609 rev 3 21/37 2.5 electrical characteristics curves figure 17. off-state output current figure 18. high-level input current figure 19. input voltage clamp figure 20. low-level input voltage figure 21. high-level input voltage figure 22. hysteresis input voltage 4c; ?#= )loff;n!= '!0'#&4 4c; ?#= )i h;u!= '!0'#&4 7jo7 4c; ?#= 6icl;6= '!0'#&4 *jon" 4c; ?#= 6il;6= '!0'#&4 4c; ?#= 6ih;6= '!0'#&4 4c; ?#= 6ihyst;6= '!0'#&4
electrical specifications vn5e160as-e 22/37 doc id 15609 rev 3 figure 23. on-state resistance vs. t case figure 24. on-state resistance vs. v cc figure 25. undervoltage shutdown figure 26. turn-on voltage slope figure 27. i limh vs. t case figure 28. turn-off voltage slope 4c; ?#= 2on;m/hm= )out! 6cc6 '!0'#&4 6cc;6= 2on;m/hm= '!0'#&4 5d?$ 5d?$ 5d?$ 5d?$ 4c; ?#= 6usd;6= '!0'#&4 4c; ?#= d6outdt /n;6ms= 6cc6 2l '!0'#&4 4c; ?#= )li mh;!= 6cc 6 '!0'#&4 4c; ?#= d6outdt /ff;6ms= 6cc6 2l '!0'#&4
vn5e160as-e electrical specifications doc id 15609 rev 3 23/37 figure 29. high-level cs_dis voltage figure 30. cs_dis voltage clamp figure 31. low-level cs_dis voltage 4c; ?#= 6csdh;6= '!0'#&4 4c; ?#= 6csdcl;6= '!0'#&4 *jon" 4c; ?#= 6csdl;6= '!0'#&4
application information vn5e160as-e 24/37 doc id 15609 rev 3 3 application information figure 32. application schematic 3.1 gnd protection network against reverse battery 3.1.1 solution 1: resistor in the ground line (r gnd only) this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1. r gnd 600 mv / (i s(on)max ). 2. r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. power dissipation in r gnd (when v cc < 0: during reverse battery situations) is: equation 1 p d = (-v cc ) 2 / r gnd this resistor can be shared amongst several different hsds. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not shared by the device ground then the r gnd produces a shift (i s(on)max * r gnd ) in the input thresholds and the status output 6 ## '.$ /54 $ '.$ 2 '.$ $ ld m # 6 6 '.$ #3?$)3 ). 2 prot 2 prot #3 2 prot 2 3%.3% # ext '!0'#&4
vn5e160as-e application information doc id 15609 rev 3 25/37 values. this shift varies depending on how many devices are on in the case of several high- side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then st suggests to utilize solution 2 (see section 3.1.2: solution 2: a diode (dgnd) in the ground line ). 3.1.2 solution 2: a diode (d gnd ) in the ground line a resistor (r gnd = 1 k ) should be inserted in parallel to d gnd if the device drives an inductive load. this small signal diode can be safely shared amongst several different hsds. also in this case, the presence of the ground network produces a shift ( 600 mv) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. this shift not varies if more than one hsd shares the same diode/resistor network. 3.2 load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the v cc max dc rating. the same applies if the device is subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. 3.3 mcu i/os protection if a ground protection network is used and negative transients are present on the v cc line, the control pins is pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the microcontroller i/o pins to latch-up. the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of microcontroller i/os. equation 2 -v ccpeak / i latchup r prot (v oh c - v ih - v gnd ) / i ihmax calculation example: for v ccpeak = - 100 v, i latchup 20 ma, v oh c 4.5 v 5 k r prot 180 k . recommended values: r prot =10 k , c ext = 10 nf.
application information vn5e160as-e 26/37 doc id 15609 rev 3 3.4 current sense and diagnostic the current sense pin performs a double function (see figure 33: current sense and diagnostic ): current mirror of the load current in normal operation, delivering a current proportional to the load one according to a known ratio k x . the current i sense can be easily converted to a voltage v sense by means of an external resistor r sense . linearity between i out and v sense is ensured up to 5 v minimum (see parameter v sense in table 9: current sense (8 v < v cc < 18 v) ). the current sense accuracy depends on the output current (refer to current sense electrical characteristics table 9: current sense (8 v < v cc < 18 v) ). diagnostic flag in fault conditions , delivering a fixed voltage v senseh up to a maximum current i senseh in case of the following fault conditions (refer to truth table ): ? power limitation activation ?overtemperature ? short to v cc in off-state ? open-load in off-state with additional external components. a logic high-level on cs_dis pin sets at the same time all the current sense pins of the devices in a high-impedance-state, thus disabling the current monitoring and diagnostic detection. this feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and adc line among different devices. figure 33. current sense and diagnostic -ain-/3n 6 /54n ) ,offr 2 3%.3% 2 02/4 4ou#!$# 2 0$ 2 05 6 05 0wr?,im 6 3 % . 3 % 05?#-$ /vertemperature /,/&& 6 /, #522%.4 3%.3%n ) /54 + 8 ) 3%.3%( 6 "!4 ) ,offf 6 3%.3%( ,oad ).054n 6 ## '.$ #3?$)3 '!0'#&4
vn5e160as-e application information doc id 15609 rev 3 27/37 3.4.1 short to v cc and off-state open load detection short to v cc a short-circuit between v cc and output is indicated by the relevant current sense pin set to v senseh during the device off-state. small or no current is delivered by the current sense during the on-state depending on the nature of the short-circuit. off-state open-load with external circuitry detection of an open-load in off-mode requires an external pull-up resistor r pu connecting the output to a positive supply voltage v pu . it is preferable v pu to be switched-off during the module standby-mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. an external pull-down resistor r pd connected between output and gnd is mandatory to avoid misdetection in case of floating outputs in off-state (see figure 33: current sense and diagnostic ). r pd must be selected in order to ensure v out < v olmin unless pulled up by the external circuitry: equation 3 r pd 22 k is recommended. for proper open load detection in off-state, the external pull-up resistor must be selected according to the following formula: equation 4 for the values of v olmin ,v olmax , i l(off2)r and i l(off2)f (see table 10: openload detection (8 v < v cc < 18 v) . v v i r v min ol f ) off ( l pd off _ up pull out 2 2 = < ? = ? () ( ) () v v r r i r r v r v max ol pd pu r ) off ( l pd pu pu pd on _ up pull out 4 2 = > + ? ? ? ? = ?
application information vn5e160as-e 28/37 doc id 15609 rev 3 3.5 maximum demagnetization energy (v cc = 13.5 v) figure 34. maximum turn-off current versus inductance (for each channel) (1) 1. values are generated with r l =0 . in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves a and b. )! ,m( '!0'#&4 c: t jstart = 125 c repetitive pulse a: t jstart = 150 c single pulse b: t jstart = 100 c repetitive pulse a b c 'hpdjqhwl]dwlrq 'hpdjqhwl]dwlrq 'hpdjqhwl]dwlrq w 9 ,1 , / *$3*&)7
vn5e160as-e package and pcb thermal data doc id 15609 rev 3 29/37 4 package and pcb thermal data 4.1 so-8 thermal data figure 35. so-8 pc board (1) 1. layout condition of r th and z th measurements (pcb: fr4 area = 4.8 mm x 4.8 mm, pcb thickness = 2 mm, cu thickness = 35 m, copper areas: from minimum pad lay-out to 2 cm 2 ). figure 36. r thj-amb vs pcb copper area in open box free air condition ("1($'5 60 70 80 90 100 110 0 0.5 1 1.5 2 2.5 rthj_amb(c/w) pcb cu heatsink area (cm^2)
package and pcb thermal data vn5e160as-e 30/37 doc id 15609 rev 3 figure 37. so-8 thermal impedance junction ambient single pulse equation 5: pulse calculation formula where = t p /t figure 38. thermal fitting model of an hsd in so-8 (1) 1. the fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cyc ling during thermal shutdown) are not triggered. 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zt h (c /w) footprint 2 cm 2 z th r th z thtp 1 ? () + ? = *$3*&)7
vn5e160as-e package and pcb thermal data doc id 15609 rev 3 31/37 table 15. thermal parameters area/island (cm 2 )footprint2 r1 (c/w) 1.2 r2 (c/w) 6 r3 (c/w) 3.5 r4 (c/w) 21 r5 (c/w) 16 r6 (c/w) 58 28 c1 (w.s/c) 0.0008 c2 (w.s/c) 0.0016 c3 (w.s/c) 0.0075 c4 (w.s/c) 0.045 c5 (w.s/c) 0.35 c6 (w.s/c) 1.05 25
package and packing information vn5e160as-e 32/37 doc id 15609 rev 3 5 package and packing information 5.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 5.2 package mechanical data figure 39. so-8 package dimensions ) ' 0 eh ( h / 6 f & d e d d $ ("1($'5
vn5e160as-e package and packing information doc id 15609 rev 3 33/37 table 16. so-8 mechanical data dim. mm. min. typ. max. a 1.75 a1 0.1 0.25 a2 1.65 a3 0.65 0.85 b0.35 0.48 b1 0.19 0.25 c 0.25 0.5 c1 45 (typ.) d4.8 5 e5.8 6.2 e1.27 e3 3.81 f3.8 4 l 0.4 1.27 m 0.6 s 8 (max.) l1 0.8 1.2
package and packing information vn5e160as-e 34/37 doc id 15609 rev 3 5.3 packing information figure 40. so-8 tube shipment (no suffix) figure 41. so-8 tape and reel shipment (suffix ?tr?) & % $ ("1($'5 all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a 3.2 b 6 c ( 0.1) 0.6 7$3(',0(16,2 16 !ccordingto%lectronic)ndustries!ssociation %)! 3tandardrev !&eb !lldimensionsareinmm 7dshzlgwk 7ds hk r o hvs dfl q j &rpsrqhqwvsdflqj +rohgldphwhu +rohgldphwhu +rohsrvlwlrq &rpsduwphqwghswk +rohvsdflqj 4o p cover tape %nd 3tart .o components .ocomponents #omponents mmmin mmmin %mptycomponentspockets saledwithcovertape 5serdirectionoffeed 5((/ ',0(16,216 !lldimensionsareinmm %dvhtw\ %x o nt w \ $pd[ %p l q &? ) * 1plq 7pd[ '!0'#&4 3? ' 'plq ) ? .pd[ 3? 3 :
vn5e160as-e order codes doc id 15609 rev 3 35/37 6 order codes table 17. device summary package order codes tube tape and reel so-8 vn5e160as-e VN5E160ASTR-E
revision history vn5e160as-e 36/37 doc id 15609 rev 3 7 revision history table 18. document revision history date revision changes 28-apr-2009 1 initial release. 25-jan-2010 2 updated table 10: openload detection (8 v < v cc < 18 v) . 25-may-2011 3 table 9: current sense (8 v < v cc < 18 v) : ?t dsense2h : updated typical and maximum values
vn5e160as-e doc id 15609 rev 3 37/37 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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